Apple's R&D centre in Munich, Germany is seeking Physical Design Engineers (Both SoC & AMS) to develop future Processors in the EU.

If you are located within the EU and want to explore these opportunities, then drop me a line.

Job Summary
Experience with Place & Route tools Synopsys or Cadence.
Familiar with hierarchical design approach, top-down design, timing and physical convergence.
In-depth understanding of STA, extensive know-how in clock/power distribution, analysis, as well as RC extraction and correlation.
Experience with SoC practices, multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration.
Scripting and programming using several of the following: Perl, TCL and Experience with large SoC designs (>20M gates) with frequencies in excess of 1GHZ beyond.
Knowledge of Verilog.

- Implementation of design partition(s) (netlist to delivery of our final GDS) for a highly complex SoC utilizing state of the art process technology
- Own block level PnR, floor-planning, clock & power distribution
- Do power and noise analysis (EM / IR-Drop / Xtalk) as well as layout verification (DRC / LVS)
- Developing/validating high performance low power clock network guidelines
Education BSEE, MSEE