You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!

  • IEDM 2018 - ASML EUV Update

    At IEDM last week Anthony (Tony) Yen, Vice President and Head, Technology Development Centers Worldwide for ASML presented a paper entitled “EUV Lithography at Threshold of High-Volume Manufacturing” authored by Anthony Yen, Hans Meiling, and Jos Benschop. At IEDM I had a chance to sit down with Tony and discuss the paper and the current status of EUV.

    Before I summarize my discussion with Tony, I want to comment on where I see EUV in the industry today. Leading-edge logic is going to be the first to implement EUV. Current state-of-the-art logic processes make extensive use of multi-patterning in the Middle-Of-Line (MOL) and Back-End-Of-Line (BEOL) and that is where we will see EUV implemented first. Samsung is the most aggressive in their approach with their first generation 7nm logic process utilizing EUV for 7 layers, Samsung is ramping that process up now. TSMC is offering a second generation 7nm process with 6 EUV layers and that process is due to ramp early next year. Intel has announced their 7nm process will also utilize EUV with a planned introduction date of 2020 although many observers question whether they will meet that date. I have heard the Intel process will use EUV for 6 layers, but it is still early, and I am not sure how credible that forecast is. Samsung and TSMC both have 5nm processes due to begin risk starts in late 2019 with more extensive EUV usage. Clearly EUV is on the threshold of high-volume manufacturing. In my ISS presentation from January 2018 I projected nine hundred thousand wafers will be processed with EUV in 2019 and over two million wafers in 2020. My ISS presentation is available here.

    ASML has previously announced the availability of a 250-watt EUV source and that source is now deployed in the field. What is new in the current presentation, is that systems in the field are now maintaining 250 watts. Figure 1 illustrates output power stability at multiple customer systems.
    Article: Cosmic Circuits acquisition by Cadence: IP battle with Synopsys has officially started!-iedm-2018-yen-presented-version_page_07.jpg
    Figure 1. Stable performance at >250 watts on multiple customer systems.

    New debris mitigation strategies are improving collector cleanliness. ASML has a goal of only a 0.1% degradation in the mirror per giga pulse of laser output and today is better than 0.3%.

    In late 2017 ASML announced their 125 wafers-per-hour (wph) milestone had been reached running source power at 195 watts with 96 steps, 20mJ/cm2 dose and no pellicle. Early this year throughput was improved to 140 wph at 246 watts with 96 steps, 20mJ/cm2 dose and no pellicle. Authors note, for logic devices, steps are roughly 110 per wafer and while initial EUV implementation are being done without a pellicle a pellicle is really needed. With a pellicle throughput drops to 116 wph. Figure 2 illustrates the achieved throughput.
    Article: Cosmic Circuits acquisition by Cadence: IP battle with Synopsys has officially started!-iedm-2018-yen-presented-version_page_08.jpg
    Figure 2. EUV throughput.

    In our discussions Tony mentioned that the 3400B is shipping today (the system used for the results in figure 2) and that next year the 3400C will start shipping with 170 wph throughput. The 3400C is the same source power as the 3400B but has lower overhead and better lens transmission.

    There is also work being done in improving the source power. 410 watts has been demonstrated for short bursts at the factory and ASML believes they can get to 500 watts.

    Pellicle development continues. The current polysilicon-based pellicle provides 83% transmission and has now been shown to stand up to 250 watts. Work on a 90% transmission pellicle continues.

    CD control and overlay are both excellent and customers are running 36nm pitch today.

    The current photoresist of record are Chemically Amplified Resists (CAR). Work with inorganic photoresist have shown single digit nanometer features with improved line edge roughness. Interestingly in his Keynote at IEDM, Samsung Foundry President ES Jung projected that inorganic resists would replace CAR for second generation EUV. Figure 3 illustrates the results of resist screening that shows better LER results with inorganic resist and good line/spaces down to a 20nm pitch although at a high dose of 67mJ/cm2.
    Article: Cosmic Circuits acquisition by Cadence: IP battle with Synopsys has officially started!-iedm-2018-yen-presented-version_page_24.jpg
    Figure 3. Photoresist comparison.

    EUV masks are reflective masks with complex absorber stacks. The height of the stacks creates 3D effects in the mask. There is work under way to find more absorptive materials that would allow thinner layers. Nickel and cobalt offer improved absorption but are difficult to etch. Imec is working on alloys as a possible solution.

    ASML is also gearing up to produce high numerical aperture EUV tools as a long-term solution for even finer resolution.

    In summary EUV is ramping up today as a 36nm solution for 7nm foundry logic processes. Continued improvement in systems, pellicles and photoresists should carry EUV into the mid-2020s. High-NA systems are being developed to continue further scaling into the late 2020s and beyond.