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  • Making the Move from 28nm to FinFET!

    EDACafe Mistakes Cadence Inc for Cadence Design Systems-finfet-cross-section.jpgIf you click FinFET in the Latest News: navigation bar at the top of this page you will get a list of 86 blogs that have been viewed more than 600,000 times. If you go to the last blogs on the list, meaning the first blogs to be published, you will see a three part series, “Introduction to FinFET Technology” written by Tom Dillinger (ChipGuy), starting in March of 2012. That series has been viewed more than 60,000 times and is still getting traffic. Rumor has it Tom is writing a book on FinFETs to be published later this year so the series continues (in print).

    Even though we have had FinFETs in production for quite some time now a significant amount of design work is still done on 28nm and above. Now that we have the cost effective TSMC 16FFC process and the even more cost effective (soon to be announced) TSMC 12nm, it's time to get more competitive and say good-bye to planar devices, absolutely.

    And ARM is going to help us do just that with their upcoming webinar:

    Making the move from 28nm to 16nm FinFET: easy as POP!

    Live Webinar: 9:00 am – 10:00 am PST and 5:00 – 6:00 pm PST
    January 17, 2017


    The TSMC 16FFC process is a lower cost FinFET option that targets a wide range of applications. So consequently, many ARM-based partners are interested in moving from a traditional CMOS manufacturing process technology to using the FinFET process. However, designers are unsure of the challenges that may be encountered when moving to FinFET.

    To facilitate meeting these new process challenges, ARM’s physical design group developed implementation solutions in both TSMC 28HPC+ and TSMC 16FFC, to both optimize and accelerate the implementation of ARM-based SoC designs. Using the latest ARM Cortex®-A73 processor as a case study, this webinar will summarize deep technical findings collected from a variety of implementation trials. We will share and discuss process differences, power grid creation challenges, floor planning differences (due to fin pitch requirements), key enhancements in clock tree synthesis, and revised signoff criteria.

    If you are thinking of making the move to a FinFET technology process, this is one webinar that you do not want to miss!

    And if you are designing an SoC, ARM also has a webinar for you:

    Three Tips to Maximize your SoC performance

    Live Webinar: 9:00 am – 10:00 am PST and 5:00 pm – 6:00 pm PST
    January 24, 2017


    CPU performance is highly dependent on choices such as: processor speed, cache size, interconnect, memory speed, data ordering, data width and optimal integration of the IP blocks. In addition to focusing on the CPU, ARM also fulfills extensive system performance analysis work to ensure that the optimal configuration options are chosen by the designer.

    Join this free webinar to understand more about the methodologies and analysis techniques used at ARM, plus how these link to CPU performance. This webinar will introduce some of the SoC design work carried out by ARM, with data for SoCs targeting mobile and server/networking applications.

    If you can’t make it to the live versions, still register and they will send you a link to the replay. I can also have SemiWiki bloggers attend them so they can share their opinions, observations, and experiences.