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  • 7nm node is arriving, which ones will continue past 2020?

    ‘Laughing Buddha’ is eternal, but for semiconductor industry, I must say it’s ‘laughing Moore’. Moore made a predictive hypothesis and the whole world is inclined to let that continue, eternally? When we were at 28nm, we weren’t hoping to go beyond 20/22nm; voices like ‘Moore’s law is dead’ started emerging. Today, we are already into production at 16nm and 14nm, and looking at 10nm, 7nm, 5nm, 3nm, and even lower going forward.
    Article: SOC Prototyping with FPGAs from a Smaller Vendor-ge_finfet.jpg
    Well, there is a large contribution of FinFET transistor structure in scaling the semiconductor technology to 16nm/14nm. FinFET along with high mobility materials like III-V and Ge for its channel can pull the node up to 10nm, may be 7nm, but not beyond that.

    Article: SOC Prototyping with FPGAs from a Smaller Vendor-gaa2.jpg

    For 5nm or even for 7nm, foundry experts are gearing up to develop further next-generation transistors, the front runner among them seems to be what is called ‘Gate-All-Around’ (GAA) transistor.
    Article: SOC Prototyping with FPGAs from a Smaller Vendor-multigatmosfet.jpg
    If we look at the evolution of transistor structure through gate, it appears to be progressing pretty much in line starting from single gate to double gate, tri-gate/FinFET and now GAA. However, it’s extremely difficult, expensive and time consuming to experiment fabrication of such complex structures and with newer material compositions. Fabricating transistors is one part of the process, often called FEOL (Front-End-Of-Line) process. BEOL (Back-End-Of-Line) process is to do all the interconnections, and there comes the complex part of managing the RC. Again, there are local interconnects at device level accomplished by MOL (Middle-Of-Line) process. The global interconnects are done by BEOL and they are prone to RC delays. Today at lower nodes, BEOL employs multiple patterning which requires extra deposition and etching with every pattern, thus increasing the cost of production. Technically, multiple patterning can still be viable at 7nm, however the industry is looking at EUV (Extreme Ultra Violet) lithography to reduce that cost; with EUV, BEOL process can be done with single exposure and throughput can be as good as ~150 wafers per hour. But for EUV lithography, foundries are dependent on semiconductor equipment manufacturing companies. To accelerate EUV lithography, Samsung, Intel and Applied Materials are reported to fund Inpria Corporation, a pioneer in high-resolution photoresist development and materials for emerging semiconductor patterning technologies. Recently, Inpria patented a technology in which inorganic photoresists provided nano-scale imaging below 20nm. By the way, aBeam Technologies is reported to have developed a technology to fabricate test patterns with minimum line-width of 1.5nm which can be used to test metrological equipments with ultra-high precisions.

    Nevertheless, if we see the roadmap of big ones, Intel, GlobalFoundries, Samsung, TSMC, UMC, all plan to bring 10nm chips latest by 2017. Daniel Nenni even blogged about Intel’s plan to launch 10nm chips in early 2017.

    TSMC is much aggressive on 7nm as well. According to ASML, TSMC has already ordered for EUV scanners to be purchased in 2015 and they are expected to start 7nm chip production in early 2018. Intel does not seem to be behind either; it plans to go ahead with 7nm, even without EUV if that’s not ready. So, let’s take some delay into account and say 7nm comes out in 2019. That translates to roughly two years gap for every major production node.

    Article: SOC Prototyping with FPGAs from a Smaller Vendor-volume_vs_node.jpg

    Above graph clearly shows 90nm, 65nm, 45nm, 32nm, 22nm, 14nm and 10nm to have around two years gap in every succession. 32nm/28nm was an inflection point below which it really was difficult to scale down. Double patterning and then multiple patterning started taking place. FinFET was invented, and now we are looking at GAA and other innovative transistor structures, EUV, and so on to go below 10nm. 7nm may arrive in 2018, 2019. Let’s say 5nm and 3nm also arrives past 2020 with support from EUV, GAA and other innovation as required. Then what? Which nodes will survive? Definitely, a few of them will have long maturity curve with major production volumes. It needs clever and strategic planning for fabs to reap the benefits from them; they will become the cash cows in the long-run. Let’s look at design starts per node as of 2013 (courtesy Synopsys) –

    Article: SOC Prototyping with FPGAs from a Smaller Vendor-design_per_node_2013.jpg

    We can clearly see 350nm - 90nm in declining mode, 65nm – 32nm still moving towards maturity and 22nm – 14nm in growth mode. If we extrapolate this trend to 7nm and then 5nm and 3nm beyond 2020, we can envision that by that time 14nm and 10nm will be in major production. Will they continue for long? I would think so, because the FinFET process will be perfected by then with 16nm, 14nm and 10nm adopting the same technology with improved performance. If GAA and other technologies get perfected by say 2025, they may take over by 2030. Beyond that we need to again look at our ‘laughing Moore’!